module dequeueMuxer4 (
    input wire clk,
    input wire rst,
    input wire dequeue_vld_1,
    input wire [5:0] dequeue_priority_1,
    input wire [9:0] dequeue_value_in_1,
    input wire dequeue_vld_2,
    input wire [5:0] dequeue_priority_2,
    input wire [9:0] dequeue_value_in_2,
    input wire dequeue_vld_3,
    input wire [5:0] dequeue_priority_3,
    input wire [9:0] dequeue_value_in_3,
    input wire dequeue_vld_4,
    input wire [5:0] dequeue_priority_4,
    input wire [9:0] dequeue_value_in_4,
    output reg dequeue_vld_out,
    output reg [5:0] dequeue_priority_out,
    output reg [9:0] dequeue_value_out
);
    wire [3:0] enqueue_arbitration;

    always @(posedge clk) begin
        //将输出信号进行复位
        if (rst) begin
            dequeue_vld_out <= 1'b0;
            dequeue_priority_out <= 0;
        end
        else begin
            if (enqueue_arbitration == 4'b0001) begin
                dequeue_vld_out <= 1'b1;
                dequeue_priority_out <= dequeue_priority_1;
                dequeue_value_out <= dequeue_value_in_1;
            end

            if (enqueue_arbitration == 4'b0010) begin
                dequeue_vld_out <= 1'b1;
                dequeue_priority_out <= dequeue_priority_2;
                dequeue_value_out <= dequeue_value_in_2;
            end

            if (enqueue_arbitration == 4'b0100) begin
                dequeue_vld_out <= 1'b1;
                dequeue_priority_out <= dequeue_priority_3;
                dequeue_value_out <= dequeue_value_in_3;
            end

            if (enqueue_arbitration == 4'b1000) begin
                dequeue_vld_out <= 1'b1;
                dequeue_priority_out <= dequeue_priority_4;
                dequeue_value_out <= dequeue_value_in_4;
            end

            if (enqueue_arbitration == 4'b0000) begin
                dequeue_vld_out <= 1'b0;
            end
        end
    end
    
    priorityArbiter4 arb(.write_en_1(dequeue_vld_1), .priority_1(dequeue_priority_1), .write_en_2(dequeue_vld_2), .priority_2(dequeue_priority_2), .write_en_3(dequeue_vld_3), .priority_3(dequeue_priority_3), .write_en_4(dequeue_vld_4), .priority_4(dequeue_priority_4), .priority_arbitration(enqueue_arbitration));
endmodule